1. Field of the Invention
This invention is related to the field of electronic circuit simulation and, more particularly, to the simulation of memories.
2. Description of the Related Art
Circuit simulation tools provide a way for the circuit designer to simulate the behavior of a complex design, identify any problems, and make alterations and enhancements to the circuit before arriving at a final design. The iterative design process has in turn improved the reliability of the end products that incorporate a given circuit design. One of the most popular circuit simulation tools is the Simulation Program with Integrated Circuit Emphasis (or SPICE). Many commercial versions of SPICE are available. In addition to SPICE-like simulators, functional simulators (which primarily are used to verify logical function of circuits) are often used, such as high level description language (HDL) simulators. HDL simulators include both event-driven simulators and cycle-based simulators.
While considered highly accurate, traditional SPICE is typically too slow for the analysis of large circuits, as the single design matrix that SPICE uses to solve the system of equations describing the circuit can grow quadratically with the number of circuit elements. To work around this limitation, so called “Fast-Spice” simulators in part achieve greater speed by intelligently partitioning a single design matrix into many smaller matrices. These small partition matrices are solved independently, and their solutions combined to form an overall solution. Design partitioning is often based on either channel-connected components or user-defined design hierarchy. A channel-connected component consists of non-linear elements which are graph-connected through their channel terminals, along with graph-connected linear elements.
One type of simulation that is computationally expensive (both in processor execution time and simulation memory requirements) is a simulation of a memory design. The memory design includes many transistors, each of which is a non-linear element that must be evaluated in each time step via various numerical methods. In order to reduce the effort, some simulators have either simulated a column of the memory and copied the results to other columns, or have reduced the model to only two columns (one storing a logical one and the other storing a logical zero in each bit cell in the column) and have extrapolated the results to other columns. In either case, the model is large because each bit cell in the column includes non-linear elements that must be simulated.